Biography

Jiaxin Liu is currently a Professor in the University of Electronic Science and Technology of China (UESTC).

He received the B.S. degree from Shandong University, Jinan, China, in 2010, and the M.S. and Ph.D. degrees from the UESTC, Chengdu, China, in 2013 and 2018, respectively. From 2015 to 2017, he was a Joint Ph.D. Student with the University of Texas (UT) at Austin, Austin, TX, USA. From 2019 to 2021, he was a Post-Doctoral Researcher with Tsinghua University, Beijing, China.

He was a recipient of the First Prize of Academic Scholarship in UESTC for the consecutive years from 2012 to 2015, the China National Scholarship in 2012, the First Prize of VeriSilicon Circuits Design Competition in 2015, and the China CSC Scholarship in 2015.

His research interest is on analog and mixed-signal integrated circuits design, with special focus on energy-efficient analog-to-digital conveters (ADCs). He has published over 10 ISSCC/JSSC papers on ADC design, with 6 ISSCC/JSSC papers as the first author.

Recent News

  • 06/2021: 1 first-author paper on noise-shaping SAR ADC with 2nd-order MES is accepted to JSSC.
  • 04/2021: 1 co-authored paper on time-interleaved noise-shaping SAR ADC is accepted to JSSC.
  • 03/2021: Jiaxin joins UESTC as a Professor. Positions for Post-Doc researchers and PhD/Master students are open. Welcome your emails!
  • 11/2020: Jiaxin gives an online lecture on “error suppression techniques for high-resolution SAR ADC”, in IEEE ICTA 2020.
  • 10/2020: 1 first-author and 2 co-authored papers are accepted to ISSCC 2021! Cheers!
  • 10/2020: 1 invited review paper on “error suppression techniques for high-resolution SAR ADC” is accepted to Journal of Semiconductor!
  • 08/2020: 1 first-author and 3 co-authored papers are accepted to JSSC!
  • 01/2020: 1 co-authored paper on time-interleaved noise-shaping SAR ADC is accepted to CICC 2020. Congratulations!
  • 11/2019: Jiaxin gives a talk on “energy-efficient ADC design with nanometer CMOS process”, in UESTC, Chengdu.
  • 10/2019: 1 co-authored paper on noise-shaping SAR ADC is accepted to ISSCC 2020. Congratulations!
  • 10/2019: 2 first-author papers on noise-shaping SAR ADC and kT/C noise cancelling SAR ADC are accepted to ISSCC 2020. Cheers!

Recent Research Works

1. 4th-Order noise-shaping SAR ADC with robust and sharp NTF ( ISSCC 2021)

The prior noise-shaping SAR ADCs rely on closed-loop charge transferring or passive charge sharing. The former is power consuming, and the latter suffers from limited noise suppression or PVT variation. In this work, we propose an efficient new integrator technique. This integrator doesn’t require any amplifier, thus is power efficient and PVT robust. It also avoids the large signal attenuation caused by passive charge sharing, therefore it can build a noise-shaping SAR ADC with sharp NTF and strong noise suppression. It has low hardware complexity, and is easy for high order extension. A 4th-order noise-shaping SAR ADC is realized based on this integrator. It measures 93dB SNDR over 250kHz bandwidth with 340uW power consumption, leading to a schreier FoM of 182dB.

2. ADC with kT/C noise cancellation ( ISSCC 2020, JSSC 2020)

As any ADC with a front-end S/H, SAR ADC suffers from a fundamental SNR challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor has to be sufficiently large. This work presents a SAR ADC with a kT/C noise cancellation technique. It enables the substantial reduction of ADC input capacitance but without large kT/C noise penalty, greatly relaxing the requirement for the ADC input driver and reference buffer.

3. Noise-shaping SAR ADC ( ISSCC 2020)

This work presents a 90dB-SNDR passive NS SAR with 2nd-order mismatch error shaping. It has an efficient architecture that removes the residue sampling and realizes 4× passive gain, leading to reduced total kT/C and comparator noise. Moreover, it realizes 2nd-order MES that is tone-free and supports full input range.

4. CT Delta-Sigma ADC ( VLSI 18 & JSSC 19)

This work presents a compact and power efficient third-order continuous-time (CT) Delta-Sigma (∆Σ) ADC with a single OTA. A 4-bit second-order fully passive noise-shaping SAR ADC is employed as the quantizer while inherently provides two additional noise shaping orders.

Publications

Journal Papers:

  1. Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang and Nan Sun, “A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4x Passive Gain and Second-Order DAC Mismatch Error Shaping”, IEEE Journal of Solid-State Circuits (JSSC), accepted.
  2. Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, and Nan Sun, “A 13-bit 0.005mm^2 40-MS/s SAR ADC with kT/C Noise Cancellation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 12, pp. 3260-3270, 2020. (ISSCC invited submission)
  3. Jiaxin Liu, Xiyuan Tang, Linxiao Shen, Shaolan Li, Zhelu Li, Wenjuan Guo, Nan Sun， “Error suppression techniques for energy-efficient high-resolution SAR ADCs”, Journal of Semiconductors (JoS), vol. 41, no. 11, pp. 111403, 2020.
  4. Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, and Nan Sun, “A 0.029-mm^2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer”, IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 2, pp. 428-440, 2019. [pdf]
  5. Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, and Nan Sun, “Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters”, IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 66, no. 4, pp. 1342-1354, 2019. [pdf]
  6. Jiaxin Liu, Guangjun Wen, Nan Sun, “Second-order DAC MES for SAR ADCs”, IET Electronics Letters, vol. 53, no. 24, pp. 1570-1572, 2017. [pdf]
  7. Jiaxin Liu, Liangbo Xie, Chuan Yin, Yao Wang, Guangjun Wen, “An all-CMOS self-compensated relaxation oscillator”, Analog Integrated Circuits and Signal Processing, vol. 82, no. 1, pp. 241-249, 2015.
  8. Chen-Kai Hsu, Xiyuan Tang, Jiaxin Liu, Ray Xu, Wenda Zhao, Abhishek Muhkerjee, Tim Andeen, and Nan Sun, “A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping,” IEEE Journal of Solid-State Circuits (JSSC), accepted (CICC invited submission).
  9. Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, and Nan Sun, “A 13.5-ENOB, 107-uW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier,” IEEE Journal of Solid-State Circuits (JSSC), accepted. (ISSCC invited submission)
  10. Dengquan Li, Zhangming Zhu, Jiaxin Liu, Haoyu Zhuang, Yintang Yang, Nan Sun, “A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration”, IEEE Journal of Solid-State Circuits (JSSC), accepted.
  11. Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P Williams, Jiaxin Liu, Zhichao Tan, Neal A Hall, David Z Pan, Nan Sun, “An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter”, IEEE Journal of Solid-State Circuits (JSSC), accepted.
  12. Haoyu Zhuang, Wenjuan Guo, Jiaxin Liu, He Tang, Zhangming Zhu, Long Chen, and Nan Sun, “A Second-Order Noise-Shaping SAR ADC with Passive Integrator and Tri-Level Voting”, IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 6, pp. 1636-1647, 2019.

Conference Papers

  1. Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun, “A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 369-371, Feb. 2021. [pdf]
  2. Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, and Nan Sun, “A 13b 0.005mm^2 40MS/s SAR ADC with kT/C Noise Cancellation”, IEEE International Solid-State Circuits Conference (ISSCC), pp. 258-260, Feb. 2020. [pdf]
  3. Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, and Nan Sun, “A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-order Mismatch Error Shaping,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 158-160, Feb. 2020. [pdf]
  4. Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, and Nan Sun, “A 0.029-mm2 17-fJ/Conv.-Step CT ΔΣ ADC With 2nd-Order Noise-Shaping SAR Quantizer”, IEEE Symposium on VLSI Circuits (VLSI), pp. 201-202, June, 2018. [pdf]
  5. Jiaxin Liu, Yu Han, Liangbo Xie, Yao Wang, Guangjun Wen, “A 1-V DTMOS-based fully differential telescopic OTA”, 2014 IEEE Asia Pacific Conference on Circuits and Systems, pp. 49-52, Nov, 2014.
  6. Jiaxin Liu, Yao Wang, Liangbo Xie, Guangjun Wen, “Current reference with temperature compensation for low power applications”, Circuits and Systems, 2012 IEEE Asia Pacific Conference on Circuits and Systems, pp. 527-530, Dec, 2012.
  7. Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun, “A 0.4-to-40MS/s 75.7dB-SNDR Fully-Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 376-378, Feb. 2021.
  8. Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun, “A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 170-172, Feb. 2021.
  9. Haoyu Zhuang, Jiaxin Liu, and Nan Sun, “A Fully-Dynamic Time-Interleaved Noise-Shaping SAR ADC Based on CIFF Architecture,” IEEE Custom Integrated Circuits Conference (CICC), Mar. 2020, accepted.
  10. Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Pan, and Nan Sun, “A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier”, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020.
  11. Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal Hall, Nan Sun, “A 16fJ/conversion-step Time-Domain Incremental Zoom Capacitance-to-Digital Converter”, 2019 IEEE International Solid-State Circuits Conference (ISSCC), pp. 196-198, Feb. 2019.
  12. Dengquan Li, Jiaxin Liu, Haoyu Zhuang, Zhangming Zhu, Yintang Yang, Nan Sun, “A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration”, IEEE Custom Integrated Circuits Conference (CICC), Apr. 2019.

Book Chapters

  1. Shaolan Li, Jiaxin Liu, Wenjuan Guo and Nan Sun, “Noise-Shaping SAR ADCs”, invited book chapter in Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits, Springer, 2020.

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